Issues in the design of store buffers in dynamically scheduled processors

Processor performance can be sensitive to load-store ordering, memory bandwidth, and memory access latency. A store bu er is a mechanism that exists in many current processors to accomplish one or more of the following: store access ordering, latency hiding, and data forwarding. Di erent policies that govern store bu er behavior can a ect overall processor performance. However, the performance impact of various store bu er policies is not clearly analyzed in available literature. In this paper, we look into various store bu er issues such as i) where to place it in the pipeline, ii) when to remove a store entry from the store bu er, iii) when to allow the stores to be retired, and iv) if, when, and how to set the contention priority of memory operations. These issues are explained in detail while design and performance tradeo s are assessed. Using a variety of C, C++, and Java benchmarks, we establish how these design policies in uence performance. We nd that the policies for store entry removal and store bu er pipeline placement have a large e ect on the overall performance of a microprocessor. In addition, we see that smaller, well-designed store bu ers can achieve comparable performance to larger, basic store bu ers. Combining these results with an analysis of the benchmarks can help one fully understand the role of the store bu er and the tradeo s in-